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What is Multiplexer(Mux) in Digital Circuits, and How It Can Be Designed?


Multiplexer digital (digital) circuit is also known as “combiner or data selector”. These circuits selects one of the input from multiple inputs and transfer it directly to output. For example, you don’t want two different input signals entering your circuit at the same time, or you want to establish a hierarchical order among themselves; in this case, you will need a formation that will select one of these signals according to the condition and include it in the circuit. These formations are called multiplexers. In this context, these circuits can also be considered as switching circuits. In the image below, you can see the symbolic representation of the 2×1 Multiplexer circuit in digital circuits, the switching example and the 2×1 gate-level design. If we see the circuit on the left as a switch, its function will be the switch circuit on the right.

Looking at the circuit above, if the selection input (selective input) is at the logic-1 level, the output of the circuit connects directly with the input-1 and any changes made on the input-1 do not affect the output signal.

Multiplexer - Wikipedia
Selection InputOutput

Incresing the Number of Inputs

If you want to increase the number of inputs of your multiplexer circuit, you must simultaneously increase the width of your selection input (S) signal. For example, 1-bit S signal will be sufficient for a 2-input selector circuit, 2-bit S signal for a 4-input circuit, and 3-bit S signal for an 8-input circuit. The rule of thumb here is that your total number of entries must be written as over 2 which is denoted by an S. To be a little more exemplary:

Simulation of 4×2 Multiplexer

First of all, we will test 4×1 gate level multiplexer by using Falstadt Editor. Ports at the top which uses inverters are selection input bits, and the ports at the left side are 4 different inputs (0-1-2-3). When selection bits are “11”, AND gate at the bottom (3rd) will be activated, and when selection inputs are given as “00” , then first AND gate (0th) will be activated and data is transferred to output.

This gate level design is symbolised as “mux symbol” as follows.

Designing Multiplexter with VHDL


When designing a digital circuit, if you are working with an FPGA, you will not need to design a gate-level multiplexer, except for very special designs. The reason for this is that the tool we use to design makes the necessary transformations and optimizations for us (eg: vivado). At the same time, since there are no gates in the FPGA, even if we design at the gate level, when the code is synthesized, we will see structures called LUTs, not gates, in the FPGA.

------- Gate Level 2x1 Mux --------
signal input_0 : std_logic;
signal input_1 : std_logic;
signal sel     : std_logic;
signal output  : std_logic;

output <= (not(sel) and input_0) or (sel and input(1));

As mentioned above, if the time and space limitations for FPGA design are not very sharp and important, the above gate-level usage will not be very efficient because we do not design from a point of view such as “I should put a multiplexer here” while designing. The designs we make turn into multiplexers according to their function. After all the 3 blocks written in VHDL below are synthesized, they turn into mux and all give the same result in the simulation.

-- ------------------------------------------------------------------------------------
--  _____                         _   _           _     
-- (  _  )                       ( ) ( )         ( )    
-- | ( ) |    _     _ __    __   | |_| |  _   _  | |_   
-- | | | |  /'_`\  ( '__) /'__`\ |  _  | ( ) ( ) | '_`\ 
-- | (('\| ( (_) ) | |   (  ___/ | | | | | (_) | | |_) )
-- (___\_) `\___/' (_)   `\____) (_) (_) `\___/' (_,__/'
-- Company  : QoreHub 
-- Engineer : Berk İhsan Metin

library IEEE;

entity mux_design is
  Port ( 
    i_sel    : in  std_logic_vector(1 downto 0);  -- Selection Input Port
    o_data   : out std_logic_vector(7 downto 0)   -- Output data port
end mux_design;

architecture Behavioral of mux_design is

    -- Constants to be muxed
    constant data_0   : std_logic_vector(7 downto 0) := x"AA";
    constant data_1   : std_logic_vector(7 downto 0) := x"BB";
    constant data_2   : std_logic_vector(7 downto 0) := x"CC";
    constant data_3   : std_logic_vector(7 downto 0) := x"DD";
    o_data <= data_0 when i_sel = "00" else
              data_1 when i_sel = "01" else 
              data_2 when i_sel = "10" else 
              data_3 when i_sel = "11" else 
              (others => '0');
    with i_sel select
        o_data <= data_0 when "00",
                  data_1 when "01",
                  data_2 when "10",
                  data_3 when "11",
                  (others => '0') when others;
mux_3_if_else: process(i_sel)                    
        if(i_sel = "00") then
            o_data <= data_0;
        elsif(i_sel = "01") then
            o_data <= data_1;
        elsif(i_sel = "10") then
            o_data <= data_2;
        elsif(i_sel = "11") then
            o_data <= data_3;
            o_data <= (others => '0');
        end if;
    end process;    

Simulation Results

The simulation results will be exactly the same for all 3 types of designs. Since multiplexers are combinational logic blocks, they will not clocks to change their output.

Schematic & Synthesis Results

 The synthesis report and diagram below give exactly the same result for 3 designs.

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