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VHDL Rising Edge Detection

If you are writing a VHDL submodule and want to detect the rising edge of a specific signal, you may think that “rising_edge(my_signal)” or “my_signal’event and my_signal = ‘1’” logics come through this issue. Nevertheless, this function works only for external clock signals. If you make a definition in the code like “rising_edge(my_signal)” or “(my_signal’event and my_signal = ‘1’)”, your HDL code will not work as you wanted. Therefore, to find the rising edge, it would be better to start with the following VHDL code.

VHDL Module Design

-- ------------------------------------------------------------------------------------
--  _____                         _   _           _     
-- (  _  )                       ( ) ( )         ( )    
-- | ( ) |    _     _ __    __   | |_| |  _   _  | |_   
-- | | | |  /'_`\  ( '__) /'__`\ |  _  | ( ) ( ) | '_`\ 
-- | (('\| ( (_) ) | |   (  ___/ | | | | | (_) | | |_) )
-- (___\_) `\___/' (_)   `\____) (_) (_) `\___/' (_,__/'
--                                   
-- Company  : QoreHub 
-- Engineer : Berk Ihsan Metin
-- Mail     : berkmetin@qorehub.com
----------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity design is
 Port (
   clk        : in  std_logic;   --! Global Clock
   i_a        : in  std_logic;   --! Global Reset
   o_a_rising : out std_logic    --! Rising Edge of Input Signal "a" (i_a)
 );
   
end design;

architecture Behavioral of design is
   
   signal a_delay0 : std_logic := '0';  --! 1 clock delayed version of i_a
   signal a_delay1 : std_logic := '0';  --! 2 clock delayed version of i_a
   
begin

   --! Delaying Input Signal To Detect Rising Edge
   detect: process(clk)
   begin
      if(rising_edge(clk)) then
         a_delay0 <= i_a;
         a_delay1 <= a_delay0;
      end if;
   end process;
   o_a_rising <= a_delay0 and (not a_delay1);

   -----------------------------------------
   -------- User Defined Logic Here --------
   -----------------------------------------
   -----                               -----
   ----                                 ----
   ---                                   ---
   --                                     --
   --                                     --
   ---                                   ---
   ----                                 ----
   -----                               -----
   -----------------------------------------
   -------- User Defined Logic Here --------
   -----------------------------------------

end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_rising_edge is
--  Port ( );
end tb_rising_edge;

architecture Behavioral of tb_rising_edge is

   signal clk      : std_logic; --! Global Clock
   signal rst      : std_logic;

   signal a        : std_logic;
   signal a_rising : std_logic;

begin

   --! 100 MHz Clock Generation
   clk_gen: process  
   begin
      clk <= '0';
      wait for 5 ns;
      clk <= '1';
      wait for 5 ns;
   end process;

   --! Stimulus Generation Process
   stim: process 
   begin
      a <= '0';
      wait for 30 ns; wait until rising_edge(clk);
      a <= '1';
      wait for 40 ns; wait until rising_edge(clk);
      a <= '0';
      wait for 50 ns; wait until rising_edge(clk);
      a <= '1';
      wait for 25 ns; wait until rising_edge(clk);
      a <= '0';
      wait;
   end process;

   --! Initialize Rising Edge Detection Module 
   module_init: entity work.design
      port map (
         clk        => clk,
         i_a        => a,
         o_a_rising => a_rising
      );

end Behavioral;

Simulation Results

As can can be seen from simulation results; The code that we have written captures the rising edge of an external signal and gives us a signal output in 1 clock period, regardless of the length of the input time. If the rising edge precedes the rising edge of the clock signal, the rising edge of the clock signal is expected; if it came on the rising edge of the clock signal, the output will be synchronous synchronous.

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