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Design of D-Flip-Flop (Schmeatic & VHDL)

Introduction

Structures called Flip-Flop (FF) are the most basic and indispensable memory unit of digital circuits. It is designed to store 1-bit data in each FF, and by combining them, larger memory units could be created like registers.

For example; If we want to store 1 byte (8-bit) data in our digital circuit, we can create structures called registers by adding 8 FFs one after the other. So why do we need a memory unit with a capacity of 1-bit, 8-bit, 10-bit or 20-bit? Let’s take an example to make it more concrete: you have a device in your hand and this device transfers information such as temperature, altitude, time to your FPGA card via any interface. You want to store or use this information somewhere on your card. Here, FF structures come together and do exactly this for us.

Time: 14.25 – Temperature: 58 °C – Altitude: 1520m
14.25
= 001110 001101

58 = 111010 
1520 = 001111 010100 
Info = 001110 001101 111010 001111 010100

As in the example shown above, time, temperature and altitude information can be expressed in 30-bits in total. We can store this information in a 30-bit capacity register inside our FPGA chip.

Ports

At the most basic level, D Flip Flop consists of 3 ports: Clock, D and Q. When the D-FF clock signal comes (choose one of the rising or falling edge), it transfers the value found in the D port to the Q port and is stored in the Q port until the next clock edge comes. A change in the D port during this intermediate period does not affect the Q port. In addition, the designer can reset the value on the Q port at any time by adding a reset port.

D-Flip-Flop Circuit

D-FF is an integrated circuit consisting of a combination of 4 NAND2 gates. This circuit can be configured in various ways and circuits such as T-Flip-Flop, JK-Flip-Flop can be built, but basically all of them have the same function.

Kapı Seviyesi D-FF Tasarımı

Register Structure

As seen below, register structures can be created by combining multiple D-FFs. The structure in this structure is stored as long as the clock trigger does not come.

4-bit Register

ISE Design Suite 14.7 D-FF Schematic Design:

Now let’s see and test this FF structure in a simulation environment. First, let’s create a new project on ISE. After setting the project name, save location and description, let’s select the “Schematic” option from the “Top-Level Source Type” section.

For this project, it doesn’t matter if we make any changes in this part because we will not run our project on FPGA. Let’s create our project by passing the “Project Summary” section that appears after we say next. After the project is created, let’s add a new resource by right-clicking on the FPGA device selected from the top left. After determining the name of our new resource, we add our resource by clicking next and skipping the “Summary” part.

FD Bilgileri

Next, let’s add the most basic 1-bit structure “Flip-Flops ⇒ fd” from the “Symbols” section on the left. If you want to examine the properties of the symbol before adding it, you can find the information of the structure by looking at the “Symbol Info” section below.

D-FF Şema Görünümü

After adding the input/output tags to the schematic part, we need to prepare a test bench for testing. Let’s add the VHDL test bench module and write the VHDL test bench code.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;

ENTITY DFlipFlop_DFlipFlop_sch_tb IS
END DFlipFlop_DFlipFlop_sch_tb;

ARCHITECTURE behavioral OF DFlipFlop_DFlipFlop_sch_tb IS 

   COMPONENT DFlipFlop
   PORT( 
	Clock     : in  std_logic;
	Input_D   : in  std_logic := '0'; -- Make default value as 0
	Output_Q  : out std_logic := '0' 
	);
   END COMPONENT;


signal clk   : std_logic;
signal d_in  : std_logic := '0';
signal q_out : std_logic := '0';

BEGIN

-- Create 100 MHz Clock which has preriod of 10 ns
clk_p: process
begin
	clk <= '0';
	wait for 5 ns;
	clk <= '1';
	wait for 5 ns;
end process;

   UUT: DFlipFlop 
	PORT MAP(
		Clock => clk,
		Input_D => d_in,
		Output_Q => q_out
   );

   tb : PROCESS
   BEGIN
	d_in <= '0';
	wait for 20 ns;
	d_in <= '1';
	wait for 10 ns;
	d_in <= '0';
	wait for 10 ns;
	d_in <= '1'; 
	wait for 35 ns;
	d_in <= '0';
	wait for 15 ns;
	d_in <= '1';
	wait for 20 ns;
	d_in <= '0';
      WAIT; -- will wait forever
   END PROCESS;


END;

As seen below, the “d_in” signal is transmitted to the q_out signal only on the rising edge of the clk signal, regardless of where it changes.

Test Bench Simulasyon Sonuçları

Vivado 2020.2 VHDL RTL Design

In this section, we are going to implement the “info” example we gave at the beginning of our explanation on VHDL code. First, create a new project from Vivado IDE. After specifying the project name and location, click next. After that, choose RTL(Register-Transfer-Level) Project option on the window that appears. Since we will not embed our code to the FGPA, the FPGA part we choose does not matter. 

After creating a project and adding our source code, write the following VHDL code and test bench and test it.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
Port (
    clk            : in std_logic;
    reset          : in std_logic;
    in_temperature : in  std_logic_vector(5 downto 0);
    in_altitude    : in  std_logic_vector(11 downto 0);
    in_time        : in  std_logic_vector(11 downto 0);
    out_info       : out std_logic_vector(29 downto 0)
 );
end DFlipFlop;

architecture Behavioral of DFlipFlop is

begin

DFF: process (clk, reset) 
begin
    if(rising_edge(clk)) then -- positive edge triggered
        if(reset = '1') then -- Synchronous reset
            out_info <= (others => '0'); -- Makes all bits zero
        else
            out_info <= in_time & in_temperature & in_altitude;
        end if;
    end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
--  Port ( );
end test;

architecture Behavioral of test is

component DFlipFlop 
Port (
    clk            : in std_logic;
    reset          : in std_logic;
    in_temperature : in  std_logic_vector(5 downto 0);
    in_altitude    : in  std_logic_vector(11 downto 0);
    in_time        : in  std_logic_vector(11 downto 0);
    out_info       : out std_logic_vector(29 downto 0)
 );
end component;

signal clk   : std_logic;
signal reset : std_logic;

signal s_temperature : std_logic_vector (5 downto 0) := (others => '0');
signal s_altitude    : std_logic_vector (11 downto 0) := (others => '0');
signal s_time        : std_logic_vector (11 downto 0) := (others => '0');
signal s_info        : std_logic_vector (29 downto 0) := (others => '0');

begin

DFF: DFlipFlop 
Port Map (
    clk            => clk,
    reset          => reset,
    in_temperature => s_temperature,
    in_altitude    => s_altitude,
    in_time        => s_time,
    out_info       => s_info
 );
 
 clk_proc: process -- create 25 MHz Clock
 begin
    clk <= '1';
    wait for 20 ns;
    clk  <= '0';
    wait for 20 ns;
 end process;
 
 reset <= '1', '0' after 20 ns;
 
 uut: process
 begin
    wait for 30 ns;
    s_temperature <= "111010";       -- 58 C
    s_altitude    <= "001111010100"; -- 1520 m
    s_time        <= "001110001101"; --14.25
    wait for 45 ns;
    s_temperature <= "010000";       -- 16 C
    s_altitude    <= "001001011100"; -- 1520 m
    s_time        <= "001111000000"; --14.25
    wait for 20 ns;
    s_temperature <= (others => '0');       
    s_altitude    <= (others => '0'); 
    s_time        <= (others => '0'); 
    wait;
 end process;
 
end Behavioral;

You can find the test results below. As we tested on the schematic earlier, the clock signal is transferred to input Q at D as soon as it arrives.

Simulasyon Sonuçları

The signals in the VHDL code represent registers. Since there is a 30-bit register collection in our design, we should have used 30 Flip-Flops. When we analyze the synthesis report after synthesizing the design, we can reach this result as follows.

Sentez Raporu

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