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CMOS Inverter Design with Cadence Virtuoso

Definition

In this article, we will examine how the inverter gates, one of the most indispensable parts of digital circuits, are designed at the transistor level and make an example design. As seen in the circuit on the left, CMOS inverter gates are designed by connecting 1 nmos and 1 pmos transistors one after the other as shown in the figure, and the logic-1 signal given from the Vin input at the end of the design is taken as logic-0 from the Vout output (or vice versa).


Design

Take the design parameters required for the design as shown below.

In the first step of the design, we need the aspect ratio of the transistors. For this, we can start from the threshold voltage (Vth) of the CMOS Inverter, and in an ideal inverter gate, the threshold voltage is half of the supply voltage.

After calculating the threshold voltage, we obtain the following equations by using the formula that gives the relationship between Vth and aspect ratio.

Based on the calculations we made above, we can now decide on the aspect ratios of the transistors. These ratios need to be neither too big nor too small to keep the Capacitive Effect low, while also reducing the current rates too much. So let’s choose average values: (W/L)n = 0.5 and (W/L)p = 1.6 values will suffice at this stage.

Cadence Schematic

Now, let’s draw our schematic over Cadence using the values we found and look at the simulation results. (The W/L ratio for PMOS is set to 1.6/0.35, for NMOS the W/L ratio is set to 0.5/0.35)

To test our design, let’s add a capacitor whose value can vary between 200 fF and 500 fF to the Vout output. and let’s look at the results.

As can be seen from the simulation results, the logic-1 or logic-0 value entering from the Vin port is inverted from the Vout port. In an ideal circuit, the propagation delays in these transitions from 0 to 1 are 0 seconds. However, since the program we use makes this simulation in conditions that are not ideal for us, as seen in the picture, this time is not 0 and varies according to the value of the load capacitor used. So, can we calculate this time before design?

Calculating Propagation Delay

If these delay times are of critical importance to our design, we can approximate these times at the design stage by performing the following operations.

time spent %50 transition from low to high
1.85 ns for 200 fF
time spent %50 transition from low to high
6.23 ns for 200 fF

Let’s take a look at how we can turn the circuit we designed above into a real physical circuit.

Layout Design

First of all, we will need a sketch defined in the “Standard Cell Library”. Afterwards, we will make our drawing in Cadence environment in accordance with that draft.

Standard Cell Library İçerisinden Bir Inverter Taslağı

The layout we have drawn according to the above sketch will be as follows. The ones that appear in the middle and on the right represent the parasitic effects that occur after the layout drawing. Although these parasitic effects do not disrupt the function of the design, they are capable of causing timing errors because they create a capacitive effect. We cannot see the results of these effects in the simulation we have made on the diagram, and their calculations are impossible. For this reason, post-layout simulations should also be completed and acted upon in order to obtain a completely realistic result.

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