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What is Multiplexer(Mux) in Digital Circuits, and How It Can Be Designed?

Introduction Multiplexer digital (digital) circuit is also known as “combiner or data selector”. These circuits selects one of the input from multiple inputs and transfer it directly to output. For example, you don’t want two different input signals entering your circuit at the same time, or you want to establish a hierarchical order among themselves; in this case, you will need a formation that will select one of these signals according to the condition and include it in the circuit. These formations are called multiplexers. In this context, these circuits… Daha fazlasını oku »What is Multiplexer(Mux) in Digital Circuits, and How It Can Be Designed?

Design of Common Source Amplifier with Cadence Virtuoso

Introduction Amplifiers, one of the indispensable parts of analog electronics, are circuits that enable low power/amplitude analog input signal to come out of the output in an amplified state. In these circuits, the gain is shown as Av and defined as Av = Vout/Vin. Common Source (CS) Amplifier circuits can be designed relatively easier and smaller than other amplifier circuits, both in terms of size and design. What we need for this design is 1 MOSFET transistor and 1 load element (resistor, current source etc.). CS Amp. The main feature… Daha fazlasını oku »Design of Common Source Amplifier with Cadence Virtuoso

CMOS Inverter Design with Cadence Virtuoso

Definition Design Take the design parameters required for the design as shown below. In the first step of the design, we need the aspect ratio of the transistors. For this, we can start from the threshold voltage (Vth) of the CMOS Inverter, and in an ideal inverter gate, the threshold voltage is half of the supply voltage. After calculating the threshold voltage, we obtain the following equations by using the formula that gives the relationship between Vth and aspect ratio. Based on the calculations we made above, we can now… Daha fazlasını oku »CMOS Inverter Design with Cadence Virtuoso

How to Use txt files in VHDL Test Bench?

Introduction While testing a VHDL module, the declared input/output ports should be tested as much as possible against all possible scenarios. For example, if a module you are designing has 5 input and 1 output ports, all input signal combinations that can enter these ports should be tested for a completely reliable design. However, the number of input combinations can reach hundreds of thousands, maybe millions for some designs. Of course, it is not possible for us to consider all combinations for these situations. Different methodologies are applied for such… Daha fazlasını oku »How to Use txt files in VHDL Test Bench?

MOSFET Operating Regions

NOTE: The images in the article are taken from Behzad Razavi’s “Design of Analog CMOS Integrated Circuits” Book. MOSFET type transistors consist of four terminals in total, namely gate, drain, source and body terminals. Unlike the base current of BJT transistors, MOSFETs have no gate current. There are two types of MOSFETs, N and P type. In N-type transistors, after the threshold voltage (Vth) is applied between the gate and source terminals of the transistor, the excess electrons in the N-doped region to which the source terminal is connected are… Daha fazlasını oku »MOSFET Operating Regions

Design of D-Flip-Flop (Schmeatic & VHDL)

Introduction For example; If we want to store 1 byte (8-bit) data in our digital circuit, we can create structures called registers by adding 8 FFs one after the other. So why do we need a memory unit with a capacity of 1-bit, 8-bit, 10-bit or 20-bit? Let’s take an example to make it more concrete: you have a device in your hand and this device transfers information such as temperature, altitude, time to your FPGA card via any interface. You want to store or use this information somewhere on… Daha fazlasını oku »Design of D-Flip-Flop (Schmeatic & VHDL)

VHDL Rising Edge Detection

If you are writing a VHDL submodule and want to detect the rising edge of a specific signal, you may think that “rising_edge(my_signal)” or “my_signal’event and my_signal = ‘1’” logics come through this issue. Nevertheless, this function works only for external clock signals. If you make a definition in the code like “rising_edge(my_signal)” or “(my_signal’event and my_signal = ‘1’)”, your HDL code will not work as you wanted. Therefore, to find the rising edge, it would be better to start with the following VHDL code. VHDL Module Design Testbench Simulation… Daha fazlasını oku »VHDL Rising Edge Detection